What is the difference between C-States and P-States of the CPU?

In modern processors, power management is not a single switch, but a set of coordinated mechanisms (C-States and P-States of the CPU, among others) that the operating system, firmware, and the CPU itself use to adjust power consumption, temperature, and performance in real time. This article distils and organizes that tangle of acronyms so you can understand what's happening under the hood when your computer saves power or speeds up.

Although each manufacturer and CPU family adds its own touch, the foundation is common: ACPI defines standard “states” for the system, devices, and processor. Here you'll see the differences between C-States and P-States, how they relate to G/S/D-States, what real-world impact they have on latency, why gamers and professional audiophiles often disable deep sleep, and what practical tools are available for use on Windows, Linux, and environments like ESXi.

ACPI in a nutshell

ACPI (Advanced Configuration and Power Interface) is the standard that orchestrates power in PCs and servers, and that replaced APM with greater control and granularity. It was born from the hand of Intel, Microsoft and Toshiba in the 90s and evolved to include 64-bit, multiprocessing, modern buses (PCIe, SATA, USB 3.x) and event detection (e.g., the power button).

Although ACPI is primarily used in the x86 family, it has also been deployed on other architectures. On ARM mobile devices, however, proprietary strategies are used (such as big.LITTLE and heterogeneous clusters) to balance efficiency and response depending on the load.

Global and Suspend States (G-States and S-States)

Global states describe the complete state of the system. The most important is G0/S0 (Working), where the computer is active. On recent hardware there is S0ix (substates of S0) which allow for very fine sleep modes with part of the SoC sleeping, especially in laptops.

• G0/S0: system in operation.
• G1 (Sleeping): covers S1, S2, S3 (suspend to RAM) and S4 (hibernate to disk). S3 keeps the RAM powered to resume quickly; S4 flushes memory to non-volatile storage.
• G2/S5 (Soft-off): Logical shutdown with minimum power to allow wake-up by events (keyboard, network, etc.).
• G3 (Mechanical-off): Physical shutdown; only the RTC survives per battery.

Keep in mind that The processor's C-States live within G0/S0: When the system enters G1, the CPU package is shut down and C‑States stop playing.

Device States (D-States)

ACPI also defines how peripherals sleep or wake up. D0 is equivalent to “full operation”, D1/D2 are intermediate (device-dependent) and D3 branches into Hot (with auxiliary power, responding to the bus) or Cold (completely off, not responding). This allows, for example, a network card to wake up the computer while other devices remain asleep.

T-States: Clock Modulation, the Last Resort

In addition to P and C, there is the clock modulation (T-States): a kind of PWM that suppresses internal clock pulses in a pattern (e.g., 1 out of every 8), reducing activity without changing the advertised base frequency. It is intended as a thermal or emergency countermeasure (PROCHOT) and is controlled via IA32_CLOCK_MODULATION, with causes/logs in MSR_*_PERF_LIMIT_REASONS.

Although some documents consider it “irrelevant”, in practice It keeps appearing on laptops with a fair thermal design and under sustained loads. If you see Windows reporting a “speed” below the minimum EIST, there is likely T-State active (clock gating).

M-States: Memory Savings

ACPI also provides memory states to reduce DRAM subsystem power consumption when the system is idle. M0 is normal operationM1/M2 and other modes force the memory to self-refresh and slow down the timing, reducing power with longer wake-up latencies. These are less visible to the user, but contribute to the overall savings.

Processor C-States: Sleep with Head

Let's now address the topic of the article: C-States and P-States. C-States are the idle states of the kernel or package. The higher the number, the deeper the sleep and greater savings, but also higher wake-up latency. They are requested with privileged instructions such as HLT or MWAIT (the latter can explicitly request a Cx and substatus), and the capability mapping reaches the OS via ACPI (_CST).

• C0: normal execution. This is where P‑States come into play.
• C1/C1E (Halt): the core stops, almost instant return to C0; C1E reduces consumption further.
• C2 (Stop-Clock): Clock signals are stopped, return takes a little longer.
• C3 (Sleep/Deep Sleep): L1/L2 is flushed to the last cache (LLC) and core clocks are turned off; only the essential state of the nucleus is preserved.
• C6 and above: The core can be powered down and its context saved in dedicated SRAM, bringing the core voltage down to ~0 V; upon exiting, the core state is restored. Some models expose up to C10 on recent platforms.

In addition to the C‑States per nucleus (CC‑states), there is the plane of Package C-States (PC-states) that turn off shared blocks (like the LLC) when all cores allow it. There are invalid combinations (if a core is in C0, the packet can't be in PC6), and the CPU can automatically "promote" or "demote" the tier based on target latencies and residencies.

Latency matters: C1 is abandoned in just a few dozen cycles, while C6/C7 can cost hundreds of microseconds. Hence, delay-sensitive loads (gaming, real-time audio, demanding networking) suffer if the processor frequently falls into deep sleep.

Performance P-States: Frequency and Voltage

While C-States are “sleep when there is no work,” P-States are “adjust the pace when Yes there is work, but it doesn't take the maximum”. P0 is the highest performance state (highest frequency/voltage), then come P1, P2… each with decreasing frequency-voltage pairs. These tables are declared to the OS via ACPI (_PSS) and controlled by MSRs like IA32_PERF_CTL/IA32_PERF_STATUS.

Historically the operating system asked for P-States (EIST/SpeedStep on Intel, PowerNow! on AMD), but today it is common to Hardware-controlled Performance States (HWP/Speed ​​Shift): The OS indicates a preference (performance/savings) and the CPU decides in milliseconds the exact point, with a very fine per-core granularity.

A key detail: P-States and C-States are “orthogonal”You can be at P0 (high frequency) and, upon becoming inactive, enter C6. Conversely, under sustained load at P2, there are no C-States because the core is executing (C0). This is why it's a good idea to mentally separate "frequency/voltage" (P) from "idle" (C).

From APM to ACPI: a paradigm shift

APM was the previous API managed primarily from BIOS and drivers. It allowed Turn off inactive peripherals and define simple global states, but the CPU was outside the direct control of the OS for security reasons. ACPI evolved to a richer, more standardized model, with table descriptions, granular control, and close collaboration between firmware, OS, and hardware.

How to enter and exit the C-States

When the scheduler has no threads ready, it executes HLT or MWAIT with a hint of the target C‑State; Interruptions “break” sleep and return the core to C0. Private caches are flushed at C3; context is saved to SRAM at C6 and the voltage is lowered to zero. Some CPUs implement Power Aware Interrupt Routing (PAIR) to route interrupts to already active cores (to save) or to idle cores (for performance), as appropriate.

Turbo, TDP and power limits

Processors define a TDP that the cooling system must be able to dissipate on a sustained basis (PL1: safe average power). Above, higher power windows can enter (PL2, and additional levels such as PL3/PL4 depending on the platform) for limited periods. If there is thermal and electrical headroom, the core can exceed the base frequency via Turbo, even asymmetric shape (more turbo with fewer active cores).

When temperatures exceed the threshold or the VRM/power demands it, PROCHOT can be activated and enter T-State or frequency clipping to protect the chip. This behavior is common in thin laptops.

 

Windows: Power Plans, Readings, and Counters

Windows offers plans like “Energy Savings”, “Balanced” and “High Performance”. The first tends to lower P-States aggressively and sleep soundlyThe third maintains high frequencies and avoids latency drops at the expense of efficiency. "Balanced" attempts a middle ground.

In Task Manager, “speed” is a synthetic metric that averages per core and considers modulation duty if there are T-States. It may exceed the base (Turbo) or fall below the minimum EIST (gating). For advanced telemetry, the “\Processor Information(_Total)\% Processor Performance” counter reflects the percentage of effective performance by CPU.

There are utilities to diagnose or adjust: CPU‑Z (basic data), HWiNFO (sensors), Throttlestop (clocks, C-States per core and PROCHOT/modulation control), or Park Control (core parking tuning/C‑States) that touch hidden power plan parameters (powercfg allows editing “IDLE_PROMOTE/DEMOTE”, etc.).

Linux: cpupower, turbostat and CoreFreq

In Linux, tools like CPU power show governors, frequency ranges and transition latencies; turbostat displays MSRs, core perf limit reasons (MSR_CORE_PERF_LIMIT_REASONS), and residencies by C-State; and CoreFreq provides a detailed view of absolute frequencies, C-States and Turbo per core/package.

A practical nuance: on some computers, the driver intel_idle can ignore BIOS restrictions over C‑States and use their own table. In others, the firmware “locks” the deepest C‑State allowed for the OS via MSR.

BIOS/UEFI and Profiles: Who's Really in Charge?

In the BIOS/UEFI settings they usually appear key switches: EIST/SpeedStep, TurboBoost and CPU C-StatesAdditionally, many servers allow you to choose power profiles: “Maximum Performance” (everything at its best, with minimal latencies) or “OS Controlled/Custom,” where the hypervisor or OS governs P/C-States. Selecting “OS Control Mode” delegates the intelligence to the operating system.

If you use hypervisors like ESXi, it is a good idea to combine OS Control Mode in BIOS with the “High Performance” plan of the hypervisor when the goal is to squeeze performance (for example with NSX-T, Edge Nodes, or latency-sensitive functions). In that scenario, you'll see P-State 0 more frequently and C-States limited to C0/C1; with a “Balanced” plan, the host will rely more on lower P-States and deeper C-States.

To summarize this whole C-States and P-States mess: ACPI defines the frame, C-States save power when there’s no work, P-States adjust high/low gear under load, T-States save the day in extreme heat, and M-States shave watts off memory. The key is to choose the right profile for your use., measure with the correct tools and, if necessary, set sensible limits on the depth of repose.