- CCD with up to 16 cores, L2 cache of 2 MB per core and L3 cache of 64 MB per CCD, with a V-Cache of 160 MB.
- Desktop Ryzen processors with up to 32 cores and up to 448MB of combined L3 cache in X3D variants.
- Grimlock Point and Halo: a blend of Zen 7/Zen 7c cores and performance-per-watt improvements of up to 36% at 3W.
- TSMC A14 as the target node and estimated window towards 2027-2028, with possible AM5 compatibility.
The latest leaks point to AMD Zen 7 (Grimlock) as the firm's next big step in high-performance CPUMost of the data comes from Moore's Law Is Dead And, although they fit with recent AMD moves, It's best to treat them with caution until there is official confirmation..
Among the key features repeated in several sources are the increase in cores per chiplet, the Double the L2 cache per core and the return of 3D V-Cache with greater capacity. For those updating in Spain or Europe, the possible continuation of AM5 It would be a nod to upgrades without having to change the motherboard.
What do the leaks reveal about Zen 7 (Grimlock)?
The heart of the rumor is clear: Each Zen 7 CCD would integrate up to 16 cores, double that of certain previous designs, with 2 MB of L2 per core y 64MB L3 per chiplet. This approach reinforces internal bandwidth and data proximity, pillars of AMD's cache strategy.
On desktop computers, two CCDs would allow processors of up to 32 cores. The variants X3D would add up to a 160 MB 3D V-Cache mosaic per CCDraising the effective L3 per chiplet to 224 MB and, in two CCD configurations, up to 448 MB total.
Silverton and Silverking chiplets: segmentation and caching
The Grimlock range plan would be structured with two CPU chiplets: Silverton and Silverking.
- Silverton would be the top-of-the-range model, with 16 cores and 32 MB of L2 cache. (2 MB per core), 64 MB of L3 cache and support for 160 MB V-Cache by chiplet
- Silverking would opt for 8 cores, 16 MB of L2 cache and 32 MB of L3 cache, without 3D V-Cache.
Combining two Silverton engines would open the door to top-of-the-line configurations with 32 cores and 64 threadsdoubling the total L2 to 64 MB and setting the bar for L3 cachet at figures that until recently seemed exclusive to the professional segment.
Estimated yield and CPI
Preliminary figures indicate an increase of CPI around 8% due to the cache redesign, with additional improvements of 16-20% in non-gaming workloads and significant multithreaded scaling. In MT scenarios, several sources indicate up to 67% compared to Zen 6supported by more CCD cores, better cache management and density.
It's not all about marketing: the emphasis is on latency, bandwidth, and peak handling. In practical terms, this could translate to more stable response times in content creation, compilation, simulation, and analytics.
Handhelds and portable consoles: Grimlock Point and Halo
In mobility, the APUs Grimlock Point y Grimlock Halo would mix nuclei Zen 7 and Zen 7c (and a “Low-Power” block), repeating the formula of recent generations. Configurations are being considered for 4 Zen 7 + 8 Zen 7c (Point) and 8 Zen 7 + 12 Zen 7c (Halo).
Efficiency would be key: improvements in performance per watt up to a 36% at 3 W, 32% at 7 W, 25% at 12 W y 17% at 22 WThis would directly impact ultralight equipment and handhelds, with fewer frame drops and more comfortable thermal profiles.
Manufacturing and scheduling
For CCDs, Zen 7 would target the node TSMC A14, an advanced evolution that replaces the classic “2 nm” nomenclature. The industrial fit suggests a landing that, depending on the product, It could range from the end of 2027 for mobile to 2028 for desktop and data center.
This pace is in line with a biennial release cadence and the maturity of the cutting-edge nodes, something that is also noticeable in the manufacturing cost and in the complexity of integrating more memory closer to the compute.
AI platform, ISA, and features
Several sources point to the possible AM5 compatibilityThis decision, if confirmed, would facilitate adoption in the European retail channel. At the instruction level, a new ISA set with quantization support and improvements in data preparation for accelerators.
Furthermore, AMD has already officially mentioned Zen 7 in its roadmap, anticipating a matrix motor and broader AI data formats integrated into the cores. The approach goes beyond AVX-512: the goal is to accelerate inference and pre/post-processing within the Generalist CPU.
Servers and professional scaling
In the EPYC field, the Grimlock architecture would seek scaling in cores and cache maintaining the chiplet philosophyConsistent latency and broader L3 access would be prioritized, key factors for analytical and database workloads. European data centers.
Although the exact numbers change depending on the filtration, the direction is clear: more density per CCD, Larger V-Cache and refined internal pathways to support intensive data traffic.
If the plans align, Zen 7 will arrive consolidating AMD's "cache-first" model: 16-core CCD, Duplicated L2, V-Cache on steroids, and a clear boost in AI and efficiencyFor users in Spain and Europe, the hypothetical AM5 continuity And the focus on performance per watt puts Grimlock on the radar for reasoned upgrades, without fanfare, but with substantial technical foundations.
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